Dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate is charge or capacitance in spite of parasitic capacitance and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of dynamic random access memory (DRAM) arrays continues to increase for future generations of memory devices.
The ability to densely pack storage cells, while maintaining required capacitance levels, is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
One method of maintaining, as well as increasing, storage node size in densely packed memory devices is through the use of "stacked storage cell" design. With this technology, two or more layers of a conductive material such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer, with dielectric layers sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with inter-plate insulative layers having a high dielectric constant.
However, it is difficult to obtain sufficient storage capacitance with a conventional STC capacitor as the storage electrode area is confined within the limits of its own cell area. Also, maintaining good dielectric breakdown characteristics between poly layers in the STC capacitor becomes a major concern once insulator thickness is appropriately scaled.
A variation of the above stacked capacitor structure is a stacked container (or cylindrical) cell, as disclosed in U.S. Pat. No. 5,162,248, which is hereby incorporated by reference. The container cell helps reduce the surface area required to obtain the necessary capacitance for a densely packed memory array. The size reduction of the memory cell is now, however, limited by the size of the access transistor.
In a paper entitled "Numerical Analysis of a Cylindrical Thin-Pillar Transistor (CYNTHIA)," by Miyano et al., published in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39, NO. 8, August 1992, a cylindrical thin-pillar transistor is disclosed. This structure forms an n-channel transistor with a cylindrical gate electrode around a p-type silicon pillar.
The present invention takes the concept of Miyano et al. much further by utilizing a cylindrical pillar transistor structure to construct a memory cell for memory devices and by constructing an interconnecting structure for semiconductor devices in general. The advantages of the present invention will come to light from the exemplary embodiments included in the following disclosure.